1. Field of the Invention
This invention relates to a technique of driving a plasma display panel, and more particularly to an apparatus and method for driving a plasma display panel wherein an initializing discharge can be weakened to lower a dark room brightness and an initialization time can be shortened to permit a single scanning.
2. Description of the Related Art
Generally, a plasma display panel (PDP) radiates light from phosphors excited an ultraviolet generated during a gas discharge, thereby displaying a picture including characters and graphics. Such a PDP is easy to be made into a slim and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development.
Referring to FIG. 1, a conventional three-electrode, AC surface-discharge PDP includes a scan electrode Y and a sustain electrode Z provided on an upper substrate 10, and an address electrode X provided on a lower substrate 18.
The scan electrode Y and the sustain electrode Z have transparent electrodes 12Y and 12Z, and metal bus electrodes 13Y and 13Z having a smaller line width than the transparent electrodes 12Y and 12Z and formed on one edges of the transparent electrodes 12Y and 12Z, respectively. The transparent electrodes 12Y and 12Z are formed from a transparent conductive metal, such as indium-tin-oxide (ITO), on the upper substrate 10. The metal bus electrodes 13Y and 13Z is formed from a metal such as chrome (Cr), etc. on the transparent electrodes 12Y and 12Z, respectively, and play a role to reduce a voltage drop caused by a high resistance of the transparent electrodes 12Y and 12Z.
An upper dielectric layer 14 and a protective film 16 are disposed on the upper substrate 10 on which the scan electrode Y and the sustain electrode Z are provided in parallel to each other. Wall charges generated upon plasma discharge are accumulated in the upper dielectric layer 14. The protective film 16 prevents a damage of the upper dielectric layer 14 caused by a sputtering during the plasma discharge and improves the emission efficiency of secondary electrons. This protective film 16 is usually made from magnesium oxide (MgO).
The address electrode X is crossed to the scan electrode Y and the sustain electrode Z. A lower dielectric layer 20 and barrier ribs 22 are formed on the lower substrate 18 provided with the address electrode X. The barrier ribs 22 are provided in parallel to the address electrode X and prevent an ultraviolet ray and a visible light produced during a discharge from being leaked into adjacent discharge cells. The surfaces of the lower dielectric layer 20 and the barrier ribs 22 are coated with a phosphor layer 24. The phosphor layer 24 is excited by an ultraviolet ray generated upon plasma display to produce any one of red, green and blue visible lights. An inactive mixture gas of He+Xe or Ne+Xe is injected into a discharge space defined between the upper and lower substrate 10 and 18 and the barrier rib 22.
The PDP cell having the structure as described above maintains a discharge by a surface discharge between the scan electrode Y and the sustain electrode Z after it was selected by an opposite discharge between the address electrode X and the scan electrode Y. In the PDP cell, a phosphor 24 is radiated by an ultraviolet ray generated upon sustain discharge to emit a visible light into the exterior of the cell. As a result, the PDP having the cells display a picture. In this case, the PDP controls a discharge sustain period of the cell, that is, the number of sustain discharge in accordance with a video data to thereby realize a gray scale required for an image display.
In order to express gray levels of a picture, such a PDP is driven by an address and display period-separated (ADS) system in which one frame is divided into various subfields having the number of different discharge for its driving.
Each sub-field is divided into an initialization period, a write period and a sustain period. For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60  second (i.e. 16.67 ms) is divided into 8 sub-fields. Each of the 8 sub-fields is again divided into a write period and a sustain period. Herein, the initialization period and the write period of each sub-field are equal every sub-field, whereas the sustain period is increased at a ratio of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field. As described above, the sustain period becomes different at each sub-field, so that it is possible to express gray levels of a picture.
Referring to FIG. 2, a driving waveform is largely divided into four periods, that is, a reset period for equalizing an initial condition of the panel into a predetermined state, a write period for selecting a discharge cell, a sustain period for expressing a gray scale depending upon the number of discharge and an erase period for erasing a discharge.
In the initialization period, the address electrode X and the sustain electrode Z remain at 0V during a first-half initializing operation. At this time, the scan electrode Y is coupled with a rising ramp voltage ramp1 having a slow slope from a sustain voltage Vs less than a discharge initiating voltage until a setup voltage Vr going beyond the discharge initiating voltage with respect to the sustain electrode Z. When the rising ramp voltage ramp1 is being increased, the discharge cell generates a weak initialization discharge between the sustain electrode Z and the scan electrode Y. Accordingly, a negative (−) wall voltage is accumulated in the surface of the protective film 16 provided on the scan electrode Y while a positive (+) wall voltage is accumulated in the surface of the lower dielectric layer 20 provided on the address electrode X and the surface of the protective film 16 provided on the sustain electrode Z.
During the following second-half initializing operation, a positive (+) voltage Vz is applied to all the sustain electrodes Z. Further, all the scan electrodes Y is coupled with a falling ramp voltage ramp2 having a slow slope from a sustain voltage Vs less than a discharge initiation voltage until 0V with respect to the sustain electrode Z. When the falling ramp voltage ramp2 is being decreased, all the discharge cells again generate an erase discharge between the sustain electrode Z and the scan electrode Y. Accordingly, the negative (−) wall voltage accumulated in the surface of the protective film 16 provided on the scan electrode Y and the positive (+) wall voltage accumulated in the surface of the protective film 16 provided on the sustain electrode Z are weakened. Further, a weak discharge is generated between the address electrode X and the scan electrode Y, and the positive (+) wall voltage on the surface of the lower dielectric layer 20 provided on the address electrode X is controlled into a proper condition for a write discharge in the write period.
In the write period, firstly, the scan electrode Y remains at a predetermined positive (+) voltage. Subsequently, a predetermined positive (+) write pulse Vx is applied to the address electrode X corresponding to the discharge cell to be selected, and a scan pulse Vy falling into 0V is applied to the scan electrode Y in such a manner to be synchronized with the write pulse Vx. Accordingly, at an intersection between the address electrode X and the scan electrode Y, a voltage between the surface of the lower dielectric layer 20 and the surface of the protective film 16 provided on the scan electrode Y has a value obtained by adding the positive(+) wall voltage on the surface of the lower dielectric layer 20 provided on the address electrode X to the write pulse Vx.
For this reason, at an intersection between the address electrode X and the scan electrode Y, a write discharge is generated between the address electrode X and the scan electrode Y and between the sustain electrode Z and the scan electrode Y. Accordingly, a positive (+) wall voltage is accumulated in the surface of the protective film 16 provided on the scan electrode Y at an intersection between the address electrode X and the scan electrode Y while a negative (−) wall charge is accumulated in the surface of the protective film 16 provided on the sustain electrode Z.
In the sustain period, firstly, levels of the scan electrode Y and the sustain electrode Z remain at 0V. Thereafter, a positive (+) sustain pulse Vs us is alternately applied to the scan electrode Y and the sustain electrode Z. Accordingly, at the discharge cell causing a write discharge, a voltage between the surface of the protective film 16 on the scan electrode Y and the surface of the protective film 16 on the sustain electrode Z is added by the positive (+) wall voltage accumulated in the surface of the protective film 16 on the scan electrode Y and the negative (−) wall voltage accumulated in the surface of the protective film 16 on the sustain electrode Z to go beyond a discharge initiation voltage. Therefore, the discharge cell selected by the write discharge generates a sustain discharge by a sustain pulse Vs us applied alternately.
The following erase period, the sustain electrode Z is coupled with a positive (+) erase ramp waveform Ve rising from 0V at a slow slope. At this time, at the discharge cell generating a sustain discharge, the positive (+) voltages accumulated in the surface of the protective film 16 on the scan electrode Y and the surface of the protective film 16 on the sustain electrode Z are added to the erase ramp waveform Ve. Thus, the discharge cell generating a sustain discharge causes a weak erase discharge between the sustain electrode Z and the scan electrode Y. Accordingly, the negative (−) wall voltage accumulated in the surface of the protective film 16 on the scan electrode Y and the positive (+) wall voltage accumulated in the surface of the protective film 16 on the sustain electrode Z is weakened to stop a sustain discharge.
In such an AC surface-discharge type PDP driving method, a ramp waveform is applied from a voltage controlled ramp (VCR) supply as shown in FIG. 3 in the initialization period.
Referring to FIG. 3, the VCR supply includes a rising ramp waveform supply 30 and a falling ramp waveform supply 32 connected, in parallel, to the panel, that is, the scan electrode Y. The rising ramp waveform supply 30 produces a rising ramp waveform rising from a sustain voltage Vs until a setup voltage Vr at a predetermined slope, and includes a first switch Q1 for supplying a rising ramp waveform in response to a control signal, and a first control signal generating device CS1 provided between the gate terminal and the source terminal of the first switch Q1. Further, a first capacitor C1 provided between the gate terminal and the drain terminal of the first switch Q1 is connected, in parallel, to a first resistor R1 provided between the gate terminal thereof and the first control signal generating device CS1. A common voltage source VDD is connected to the drain terminal of the first switch Q1. The first control signal generating device CS1 plays a role to apply a control signal to the gate terminal of the first switch Q1 to switch the first switch Q1.
The first capacitor C1 and the first resistor R1 set a voltage flowing, via the first switch Q1, into the panel by a RC time constant value. In other words, by this RC time constant value, a rising ramp waveform applied to the panel rises at a predetermined slope. Thus, a voltage from the common voltage source VDD rises at a predetermined slope from a sustain voltage Vs until a setup voltage Vr of 400V like the reset waveform shown in FIG. 2. Thereafter, when it falls from the setup voltage Vr of about 400V into the sustain voltage Vs of about 180V, a reverse voltage of about −70V is generated between the gate terminal and the source terminal of the first switch Q1 to damage the first switch Q1. In order to prevent this, a first diode D1 connected, in parallel, to the first resistor R1 is provided. Accordingly, a rising ramp waveform having a constant slop during a RC charge and discharge time caused by the first resistor R1 and the first capacitor C1 is applied to the panel.
The falling ramp waveform supply 32 generates a falling ramp waveform falling from the sustain voltage Vs into a ground level GND at a predetermined slope, and includes a second switch Q2 for switching the falling ramp waveform into the display panel in response to a control signal, and a second control signal generating device CS2 provided between the gate terminal and the source terminal of the second switch Q2. Further, a second capacitor C1 provided between the gate terminal and the drain terminal of the second switch Q2 is connected, in parallel, to a second resistor R2 provided between the gate terminal thereof and the second control signal generating device CS2. The drain terminal of the second switch Q2 is connected to the panel while the source terminal thereof is connected to the ground voltage source. The second control signal generating device CS2 plays a role to apply a control signal to the gate terminal of the second switch Q2 to switch the second switch Q2.
The second capacitor C2 and the second resistor R2 set a voltage flowing, via the second switch Q2, into the panel by a RC time constant value. In other words, by this RC time constant value, a falling ramp waveform applied to the panel falls at a predetermined slope. Thus, a falling ramp waveform falls at a predetermined slope from the sustain voltage Vs until the ground level GND like the reset waveform shown in FIG. 2. Thereafter, when it falls from about 180V into the ground level GND, a reverse voltage of about −70V is generated between the gate terminal and the source terminal of the second switch Q2 to damage the second switch Q2. In order to prevent this, a second diode D2 connected, in parallel, to the second resistor R2 is provided. Accordingly, a voltage applied to the panel is decreased at a constant slope with the lapse of a RC charge and discharge time from a variable resistance of the second switch Q2 and the second capacitor C2 between the drain terminal and the gate terminal thereof.
Such a system employing the voltage controlled rising and falling ramp waveforms from the VCR supply slowly increase and thereafter decrease a ramp voltage at a long ramp time to generate a weak discharge repetitively, so that it can form wall voltages and space charges in a discharge space to lower a write voltage. Also, it has an advantage in that it reduces a background light at an initialization time to improve a dark room contrast ratio.
However, when a ramp time is lengthened, an initialization time also is increased. As a result, a sustain period is reduced and hence a brightness is reduced. If a ramp time is shortened to reduce an initialization time, then a discharge current is increased to generate an oscillation at a lamp waveform due to a gap voltage between a voltage and a wall voltage applied at an opposite polarity within the discharge cell. Thus, the background light is increased by the discharge to cause an unstable discharge state, thereby raising a write failure.
Therefore, there has been required a novel driving scheme capable of restraining an oscillation of the gap voltage by controlling a discharge current depending upon a load in the discharge cell as well as reducing an initialization time without any increase of the ground light, instead of the VCR system of applying a voltage waveform given independently of a load variation in the discharge cell.